The present invention relates to a transmission circuit for transmitting signals between circuit units on a semiconductor integrated circuit, and a semiconductor memory using the same.
A transmission circuit capable of transmitting signals at high speed even through a wire long in length and large in parasitic capacitance has been desired for a semiconductor integrated circuit. In the case of a CMOS circuit, a circuit shown in FIG. 18 is known as a conventional transmission circuit. In the same drawing, reference numeral 101 indicates a dynamic CMOS circuit used as a driver circuit. Symbol W indicates an equivalent circuit of a wire in which a parasitic capacitance CL and a parasitic resistance RL are taken into consideration. Reference numeral 200 indicates an inverter used as a receiving circuit. Symbol xcfx861 indicates a control signal and Symbol IN indicates a data signal respectively. Operational waveforms of the circuit are illustrated in FIG. 19. When the control signal xcfx861 is a low potential VSS (xe2x80x98Lxe2x80x99), a precharge period is set up, whereas when the control signal xcfx861 is a high potential VDD (xe2x80x98Hxe2x80x99), an evaluation period is setup. During the precharge period, an output Q1 produced from the driver circuit 101 reaches xe2x80x98Hxe2x80x99. If the data signal IN is xe2x80x98Hxe2x80x99 (indicated by a solid line) when the control signal xcfx861 changes from xe2x80x98Lxe2x80x99 to xe2x80x98Hxe2x80x99, then the output Q1 is discharged and changed from xe2x80x98Hxe2x80x99 to xe2x80x98Lxe2x80x99. Under the influence of a time interval (CR time constant) obtained from the product of the parasitic capacitance CL and the parasitic resistance RL of the wire W, an output Q1B at the exit of the wire W changes from xe2x80x98Hxe2x80x99 to xe2x80x98Lxe2x80x99. Thereafter, the receiving circuit 201 outputs an output Q2 in response to the output Q1B at the exit of the wire W. On the other hand, if the data signal IN is xe2x80x98Lxe2x80x99 (indicated by a broken line) when the control signal xcfx861 changes from xe2x80x98Lxe2x80x99 to xe2x80x98Hxe2x80x99, then no outputs Q1 and Q1B are discharged and they are maintained at xe2x80x98Hxe2x80x99. As the parasitic capacitance of the output part Q1 increases, transistors large in gate width are used as transistors for the driver circuit 101, and the shortening of the time required to charge and discharge the output Q1 is achieved.
In the conventional transmission circuit as indicated by the operational waveforms shown in FIG. 19, the time necessary for the output Q1 of the driver circuit 101 to fall is faster and a delay time (tpd1) thereof is small. However, the waveform is rendered dull due to the influence of the parasitic capacitance and the parasitic resistance at the exit Q1B of the wire W, and a delay time (tcrf) is developed (where the logic threshold potential of the inverter constituting the receiving circuit is supposed to be a common (VDD/2)). The delay time developed due to the influence of the wire increases in proportion to the product of the parasitic capacitance and the parasitic resistance. Therefore, the delay time is so long and becomes dominant when the wire is long, and hence the performance of the semiconductor integrated circuit is rate-controlled by the delay time developed under the influence of the wire.
Incidentally, a waveform-dull phenomenon is not limited only to the case where the length of the wire is long. There may be cases in which transistors each having a small gate width, which are short in wiring length and large in parasitic capacity, are used for the driver circuit 101.
With the foregoing problems in view, it is therefore an object of the present invention to shorten the time required to transmit a data signal even when a signal waveform is made dull.
Another object of the present invention is to shorten a precharge time at an exit portion of a signal wire (transmission line) and shorten a transmission cycle time.
According to one aspect of the present invention, for achieving the above objects, there is provided a transmission circuit, comprising a driver circuit alternately controlled to a precharge period and an evaluation period according to a first control signal, the driver circuit precharging an output node to a first source potential during the precharge period and driving the output node to either one of the first source potential and a second source potential according to a potential at an input node during the evaluation period, a signal line coupled to the output node of the driver circuit so as to be driven by the driver circuit, and a receiving circuit comprising a semiconductor logic circuit, which has a first node and a second node and is alternately controlled to the precharge period and the evaluation period according to a second control signal to precharge the first and second nodes to the first source potential together during the precharge period, and discharge the second node according to a potential at the first node and discharge the first node according to a potential on the signal line during the evaluation period, thereby making a distinction as to the potential on the signal line with the potential at the first node as a reference potential. Further a signal line precharge transistor is provided at an exit portion of the signal line (transmission line).